The present invention relates to a low pass filter with adjustable bandwidth, and to a lock detector circuit that indicates the generation of a desired clock whose frequency is locked in a feedback system such as a phase locked loop or a delay locked loop.
The phase locked loop (PLL) and delay locked loop (DLL) are two representative feedback systems. A feedback system is used in a synchronous memory device to transmit data to external devices by using internal clock signals locked in synchronization with an external clock signal inputted from an external device such as a memory controller. For stable data transmission between the semiconductor memory device and the memory controller, temporal synchronization between a reference clock signal and the data is important.
The feedback system includes a lock detector circuit indicating whether the phase and frequency of a clock signal having a particular frequency are locked to those of a reference clock signal. The lock detector circuit outputs a lock signal indicating the phase locking when a phase difference between two signals is inputted to a phase frequency detector (PFD), that is, a clock signal having an arbitrary frequency and a reference clock signal, is maintained for a certain period of the reference clock signal. The lock signal indicating the locking of the feedback system is transferred to the next circuit, and an operation after PLL locking is performed.
As illustrated in FIG. 1, when the feedback system is in a locking state, output signals UP and DN of the phase frequency detector are outputted in a pulse form having a narrow pulse width (constant pulse width). However, as illustrated in FIG. 2, when the feedback system is in an unlocking state, the pulse widths of the output signals UP and DN of the phase frequency detector are rapidly increased. When the pulse widths are changed as illustrated in FIG. 2, the lock detector circuit cannot output the lock signal indicating the phase locking.
FIG. 3 is a circuit diagram of a typical low pass filter determining whether to output the lock signal in the lock detector circuit. Referring to FIG. 3, the typical low pass filter includes an NMOS transistor N1 and a PMOS transistor P2 connected in series between a power supply voltage terminal VDD and a ground voltage terminal. The NMOS transistor N1 is turned on in response to an input clock signal of a logic high level, and the PMOS transistor P2 is turned on in response to an input clock signal of a logic low level. The input clock signal is applied to gates of the two transistors N1 and P2. Furthermore, a PMOS transistor P1 is connected between the power supply voltage terminal VDD and the PMOS transistor P2 and acts as a resistive element with respect to the supply voltage. A gate of the PMOS transistor P1 is connected to the ground voltage terminal.
One terminal of a capacitor C is connected to a node NODE1 where drains of the two transistors N1 and P2 are commonly connected, and the other terminal of the capacitor C is connected to the ground voltage terminal.
In addition, a comparator using a Schmitt trigger S1 is connected to the node NODE1, and an output of the Schmitt trigger S1 is fed back to a gate of a PMOS transistor P3 connected between the power supply voltage terminal and the node NODE1. The output of the Schmitt trigger S1 is outputted as a reset signal RESET through an inverter IV1.
In operation of the typical low pass filter, the NMOS transistor N1 and the PMOS transistor P2 are turned on in response to the input clock signal of the logic high level and the input clock signal of the logic low level. The supply voltage, passing through the PMOS transistor P1 acting as the resistive element, is supplied to the node NODE1 according to the turn-on characteristics of the turned-on transistors. In this case, the supply voltage supplied to the node NODE1 is charged into the capacitor C.
Meanwhile, as illustrated in FIG. 4, when the pulse width of the input clock signal is long, the turn-on characteristics of the transistors P2 and N1 become greater than the case where the low signal is outputted from the low pass filter. Therefore, the voltage applied to the node NODE1 exceeds the limit value of the Schmitt trigger S1, despite it's passing through the RC charge/discharge circuit. In this case, the output of the low pass filter goes to a logic high level.
That is, the low pass filter filters the input pulse signal during a period where the pulse width of the input clock signal is short. When the phase locked loop is in an unlocking state, the output signals UP and DN of the phase frequency detector, which have long pulse widths, are inputted to the low pass filter. Thus, the low pass filter cannot filter the signals sufficiently and outputs a high signal. The generated high signal indicates the unlocking state of the lock detector circuit.
On the other hand, when the phase locked loop is in a locking state, the output signals UP and DN of the phase frequency detector, which have short pulse widths, are inputted to the low pass filter. Thus, the low pass filter filters the signals sufficiently and outputs a low signal. The generated low signal indicates the locking state of the lock detector circuit.
Meanwhile, when reading data from the memory device (for example, DRAM) or writing data to the memory device, data training is performed for controlling the mismatching of timing between data, and clock training is performed for controlling timing between clocks. The data training is a technology that controls timing between data by using data patterns known to the controller and the memory device when data is written to the memory device (write training) and data is read from the memory device (read training). In addition, the clock training controls the timing of clocks to be used in the memory device. The clock training operation and the data training operation are used in a specific memory device, especially, in order to increase a data valid window.
The clock training operation is controlled in the PLL locking state. However, if the reference clock is delayed with a constant value in order for the clock training, the pulse widths of the output signals UP and DN of the phase frequency detector are instantaneously increased. Thus, the low pass filter generates a high signal and performs an erroneous operation to determine that the PLL circuit is in an unlocking state.
Such an erroneous operation is also applied to a case where jitter contained in the reference clock signal or the feedback clock signal of the voltage controlled oscillator (VCO) is large, so that the phase locked loop is determined as being in an unlocking state.
Therefore, although the PLL circuit is in the locking state, the low pass filter cannot filter the signals sufficiently when the frequency variation is great, just like in the case jitter contained in the clock training operation or the reference clock signal and the feedback clock signal of the VCO is great, so that the phase locked loop performs an erroneous operation to determine the PLL circuit as being in the unlocking state.
Furthermore, due to the erroneous operation to determine the phase locked loop as being in the unlocking state, it is impossible to perform the operation after the locking of the phase locked loop.